Title :
Modeling of flip chip bump patterns to minimize crosstalk on a BU-BGA package design.
Author :
Sheach, K. ; Xiang, G. ; Brunet, Philippe
Author_Institution :
High Speed Package Design, STMicroelectronics, Inc., Nepean, ON, Canada
Abstract :
We provide a practical example of concurrent design practice employed to optimize system level design specifications. Through package level modeling it was possible to improve the performance of a die I/O assignment. 3D EM modeling of the package flip-chip interconnect revealed that a significant improvement in the differential cross talk levels could be achieved by simple re-ordering of the die pad assignments.
Keywords :
ball grid arrays; crosstalk; flip-chip devices; interconnections; microassembling; 3D EM modeling; BU-BGA package design; crosstalk minimization; die pad assignment; flip-chip bump pattern modeling; flip-chip interconnection; Clocks; Costs; Crosstalk; Design optimization; Electronics industry; Electronics packaging; Flip chip; Process design; Silicon; System-level design; Flip chip package; High-speed; Interconnect; X-talk;
Conference_Titel :
Microelectronics and Packaging Conference, 2009. EMPC 2009. European
Conference_Location :
Rimini
Print_ISBN :
978-1-4244-4722-0
Electronic_ISBN :
978-0-6152-9868-9
