Small size LTCC FlipChip-package for RF-power applications

Heat dissipation is becoming a key issue in designing packages due to growing power densities associated with IC downscaling and the introduction of new semiconductor technologies (e.g. AlGaN). Additionally, FlipChip assembly is being favoured due to small form factor and reduced interconnect parasitics which can be essential for RF and microwave applications. Compared to chip and wire technology the FlipChip approach suffers from smaller thermal interfaces since mainly the bumps contribute to the heat conduction. Minor improvements can be achieved by underfill or overmold materials. Concepts which use the entire die surface for heat conduction are based on cavity down FlipChip packages. The direct heat path from die to the circuit board is established during package mounting (e.g. soldering or gluing). However, mechanical tolerances of cavity depth, die thickness and bump height are resulting in a gap between the die surface and the board. This gap needs to be filled by a thermal interface material which degrades the thermal performance. The new wafer level compatible concept uses a back grinding step after FlipChip mounting and underfilling. The underfill seals the cavity and provides a smooth surface for the metal interconnect layer. Signal and thermal pads are achieved by sputtering and galvanic processes. This thermally enhanced package allows a six times higher power dissipation compared to a conventional LTCC Package with top side FlipChip assembly and thermal vias. The paper describes the concept and the sample preparation of alternative FlipChip packages. Simulation and measurement results are compared.