Assembly - chip interactions leading to PPM-level failures in microelectronic packages

It is known that molding compounds, containing irregularly shaped filler particles, used in microelectronic devices can cause damage within the diffusion stack. Electrical shorts between the top two metal layers often manifest this phenomenon. Such effects are usually seen in non-planarized diffusion processes due to their relatively larger irregularity in topography. The main factors that control this phenomenon are the properties of the molding compound (the filler size and shape), the mechanical integrity of the passivation layer, and the stresses in the chip. In this study, we focus on assembly - chip interactions that lead to a low PPM level failure. This is considered as unacceptable in today´s zero PPM mindset in the automotive industry. FEM simulations are performed to estimate the stresses within the backend stack of the chip. With the help of these simulations, the most sensitive locations within the structure are identified. The scaling of this stress with filler size is analyzed and compared to that obtained with a high end low thermal expansion molding compound, containing round fillers with better size control. Using estimations and measurements of the particle size distribution, flow modeling, and statistical methods, the PPM level of the failures could be attributed to the low chance that a filler particle would land on the critical location. Modulating these effects yielded some interesting interactions between assembly and chip processing, which will be described in more detail.