• DocumentCode
    503134
  • Title

    WPLGA: New package family for medium pin count with design flexibility

  • Author

    Magni, Pierangelo ; Graziosi, Giovanni ; Villa, Claudio-Maria ; Tiziani, Roberto ; Gacusan, Rodolfo

  • Author_Institution
    ST Microelectron., Agrate Brianza, Italy
  • fYear
    2009
  • fDate
    15-18 June 2009
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In this article we present a relatively new and innovative family of packages that is suitable for medium pin count needs and that locates itself between BGAs and ldquostandardrdquo QFN with single row of pads. It is characterized by the extreme design flexibility in term of I/Os size, location and shape, allowing a wide range of customization; only limited by PCB layout constraints. Nevertheless its structure looks like metal QFN, the pad-out is more similar to LGA array, being a multi-row design, with the possibility to have exposed partial/full ground and/or power rings. All this allows a relatively large footprint reduction compared with the same I/Os of a TQFP package, including a significant total package height reduction. Simplified assembly flow and easy handling leads to package total cost competitive respect to BGAs and TQFPs, allowing also testing on strip. Results from samples will be shown demonstrating good reliability characteristics, thermally in between QFNs and BGAs, and from electrical point of view good performances due to reduction of the overall signal path length die-application board. Also solder joints show an improvement respect to standard QFNs. We will show the package structure and its design options, thermal and electrical modeling data and overall package performances and possible applications. The innovative nature of this new package along with its promising results data and cost structure is proving of great interest and this new package is not moving towards mass production.
  • Keywords
    electronics packaging; BGA; TQFP; WPLGA; design flexibility; medium pin count; Assembly; Costs; Lead; Microelectronics; Packaging; Sawing; Shape; Strips; Testing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics and Packaging Conference, 2009. EMPC 2009. European
  • Conference_Location
    Rimini
  • Print_ISBN
    978-1-4244-4722-0
  • Electronic_ISBN
    978-0-6152-9868-9
  • Type

    conf

  • Filename
    5272896