DocumentCode :
503140
Title :
Trends in IC packaging
Author :
Beelen-Hendrikx, Caroline
Author_Institution :
NXP Semicond., Nijmegen, Netherlands
fYear :
2009
fDate :
15-18 June 2009
Firstpage :
1
Lastpage :
8
Abstract :
Drivers for new package development are cost reduction, form factor requirements, reliability, electrical performance and function integration. Cost reduction is realized by improvement of existing packaging platforms, such as material cost reduction, and changes in processes and design methods, and by introducing new packaging platforms. Future low cost packaging platforms will be based on batch processes, large format processing, use of low cost substrates or no substrates at all, and will avoid over specification. Embedded packaging is a new technology that is either based on wafer fab technology or PCB fab technology. Wafer fab technology based embedded packages give the highest reduction in form factor but are relatively expensive. PCB fab technology based embedded packages are less expensive but have lower definition. Therefore, they will first be used for low pin count packages. Embedding in motherboards or interposers is a way to reduce package thickness; it is expected to be mainstream for simple, low pin count products. Package reliability requirements are tightened by automotive and lighting businesses, requiring, high temperature, long lifetime and zero delamination. To meet the requirements, interfacial strength and interconnect robustness need to be improved. New functions are realised by silicon based sensors and MEMS, e.g. for automotive, medical, environmental and communication purposes. Packaging challenges include wafer treatment, MEMS protection and the realization of die access for fluids and gases to be analyzed. Function integration drives the development of 3D packaging technologies. Ultimate technology is heterogeneous integration by 3DIC. This technology optimizes electrical performance and form factor. For 3DIC ultra-thin dies are stacked by fine pitch flip chip interconnect and silicon through vias. Disadvantage is cost. Therefore, for many applications, stacked die wire-bonded IC packages are still popular. They offer improved bandwidth,- power consumption and size, and equal cost compared to separate packages. For 3DIC and also for products such as RFID tags and medical plasters, ultra-thin dies are needed. These require dedicated thinning and dicing technologies with use of temporary carriers.
Keywords :
integrated circuit packaging; micromechanical devices; radiofrequency identification; reliability; 3DIC ultrathin dies; IC packaging; MEMS protection; RFID tags; die access; fine pitch flip chip interconnect; function integration; interconnect robustness; interfacial strength; medical plasters; package reliability; silicon based sensors; silicon through vias; stacked die wire-bonded IC packages; wafer treatment; Automotive engineering; Cost function; Delamination; Design methodology; Integrated circuit packaging; Micromechanical devices; Protection; Robustness; Silicon; Temperature sensors; 3D Packaging; Cost Reduction; Embedding; Memory Integration; Reliability; Sensors & MEMS; Thin Dies;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics and Packaging Conference, 2009. EMPC 2009. European
Conference_Location :
Rimini
Print_ISBN :
978-1-4244-4722-0
Electronic_ISBN :
978-0-6152-9868-9
Type :
conf
Filename :
5272902
Link To Document :
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