Wafer level packaging fan out thermal management: Is smaller always hotter?

Actually the electronic packaging industry is developing the fan out wafer-level packaging (FO WLP) technology that shows an intrinsic capability for higher integration and relevant supply chain. Size and cost reduction, better signal integrity and higher speed compared to standard laminate BGA make this new solution very attractive. In this paper we analyze from a thermal point of view the same chip assembled in standard and flip chip BGA and in fan out WLP in order to compare the different thermal behaviours. The main advantage of this new technology is a quite low vertical thermal resistance. The present study shows thermal modeling analysis results achieved using FLOTHERM^reg. Total thermal behaviour is due to the balance between vertical thermal resistance and lateral heat spreading. Substrate thickness is determined as the dominating factor controlling the total WLP thermal resistance. The impact of die size and hot spot presence has been investigated. Different board designs are also considered.