Advanced modeling techniques for system-level power integrity and EMC analysis

In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, introducing new challenges to ensure the power integrity (PI) of the electronic systems, and increasing the electromagnetic interference (EMI). The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions and modeling techniques to assess and guarantee PI and electromagnetic compatibility (EMC) across the overall system that comprises the chip, package, and printed circuit board (PCB). Hence, PI and EMC/EMI are rapidly becoming a major concern for high-speed circuit, package, and board designers. In this work we investigate the impact of the chip power rail noise on system PI and EMI, and we show that by reducing the power rail noise thus assuring the system PI, it is possible to significantly reduce the electromagnetic (EM) conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and PCB designers to predict the power integrity and the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.