Analysis and optimization of LUDMOS transistors on a 0.18µm SOI CMOS technology

Author

Toulon, G. ; Cortés, I. ; Morancho, F. ; Villard, B.

Author_Institution

LAAS, CNRS, Toulouse, France

fYear

2009

fDate

25-27 June 2009

Firstpage

549

Lastpage

554

Abstract

This paper is focused on the design and optimization of power LDMOS transistors (V_BR > 120 Volts) with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 mum SOI-CMOS technology. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is analyzed in terms of the main static (R_on-sp/V_BR trade-off) and dynamic (Miller capacitance and Q_gtimesR_on FOM) characteristics. The influence of some design parameters such as the polysilicon gate electrode length and the STI length are exhaustively analyzed.

Keywords

CMOS integrated circuits; capacitance; isolation technology; power MOSFET; power integrated circuits; silicon-on-insulator; 3D RESURF; LUDMOS transistors; Miller capacitance; SOI-CMOS technology; STI length; polysilicon gate electrode length; power LDMOS transistors; shallow trench isolation; size 0.18 mum; smart power technology; CMOS integrated circuits; CMOS technology; Design optimization; Doping; Isolation technology; MOSFETs; Paper technology; Parasitic capacitance; Plasma displays; Transistors; LDMOS; Power MOSFET; RESURF; STI; Silicon-On-Insulator; Superjunction;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits & Systems, 2009. MIXDES '09. MIXDES-16th International Conference

Conference_Location

Lodz

Print_ISBN

978-1-4244-4798-5

Electronic_ISBN

978-83-928756-1-1

Type

conf

Filename

5289632