Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks

Author

Krishna, Tushar ; Chen, Chia-Hsin Owen ; Sunghyun Park ; Woo-Cheol Kwon ; Subramanian, Sivaraman ; Chandrakasan, Anantha P. ; Li-Shiuan Peh

Volume

46

Issue

10

fYear

2013

fDate

Oct-13

Firstpage

48

Lastpage

55

Abstract

Future scalability for kilo-core architectures requires solutions beyond the capabilities of protocol and software design. Single-cycle multihop asynchronous repeated traversal (SMART) creates virtual single-cycle paths across the shared network between cores, potentially offering significant reductions in runtime latency and energy expenditure.

Keywords

multiprocessing systems; network-on-chip; reconfigurable architectures; virtual machines; SMART; energy expenditure reduction; multicore chip architecture; reconfigurable onchip network; runtime latency reduction; scalability; single cycle multihop asynchronous repeated traversal; virtual single cycle path; Computer architecture; Design methodology; Multicore processing; Ports (Computers); Radio mobile; Scalability; System-on-chip; NoC; SoC; cache coherence traffic; efficient network design; interconnection network; multicore architecture; network-on-chip; on-chip latency; parallel computer architecture; private L2; scalability; scalable networks; shared L2; system-on-chip;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/MC.2013.260

Filename

6564277