VISTA: A new fair queuing algorithm for packet switches

Author

Xia, Yu ; Guo, Zirong ; Gao, Zhijiang

Author_Institution

Sch. of Info. Sci. & Tech., Southwest Jiaotong Univ., Chengdu, China

fYear

2009

fDate

14-16 Sept. 2009

Firstpage

1

Lastpage

8

Abstract

Fairness and QoS have been main concerns in designing modern routers or switches in multimedia environment. This paper proposes a new packet-based fair queuing algorithm for packet switches called VISTA (Virtual Clock with Virtual Start Time Alignment) to improve fairness in existing VC (Virtual Clock) algorithm. A novel concept of virtual start time alignment is introduced to improve fairness of VC algorithm and to reduce the computing complexity to constant time with a hardware-based earliest Packet Selector (EPS).

Keywords

multimedia communication; packet switching; quality of service; queueing theory; telecommunication network routing; QoS; VISTA algorithm; computing complexity; fair queuing algorithm; hardware-based earliest packet selector; multimedia environment; packet switch; router design; virtual clock-with-virtual start time alignment; Algorithm design and analysis; Computer architecture; Computer networks; Internet; Large-scale systems; Object oriented modeling; Packet switching; Protocols; Software engineering; TCPIP; Packet-based Fair Queuin; QoS guarantee; VISTA algorithm; Virtual Clock; WF2Q+;

fLanguage

English

Publisher

ieee

Conference_Titel

Broadband Communications, Networks, and Systems, 2009. BROADNETS 2009. Sixth International Conference on

Conference_Location

Madrid

Print_ISBN

978-963-9799-49-3

Electronic_ISBN

978-963-9799-49-3

Type

conf

DOI

10.4108/ICST.BROADNETS2009.7659

Filename

5336336