Low-power AES coprocessor in 0.18 µm CMOS technology for secure microsystems

This paper presents an implementation of the Advanced Encryption Standard (AES) algorithm in 0.18 µm CMOS technology. The core module was found to be low power and low area and is meant to act as a cryptographic coprocessor in microsystems requiring additional security. The design was fabricated using Canadian Microelectronics Corporation´s (CMC) digital design flow and packaged using a 40 pin Dual-inline Package. A potential system architecture using the fabricated module is also presented.