Development of a reliable low cost NMOS process for microfabrication courses and proof-of-concepts in research

We present a low cost NMOS technology designed to support undergraduate and graduate microfabrication and device physics courses. This 6 mask process is intended to be reliably fabricated in a broad access university facility using undedicated equipment. One set of cells has been designed for process characterization (including statistical analysis) and device physics analysis. A second set of cells comprises basic logic gates, binary counters and analog circuit elements including an operational amplifier. In addition to teaching purposes, the technology aims at enabling the integration of Si electronic technologies (either as control or as front-end electronic) with other technologies such as single electronics (SET), biosensors and MEMS. This is accomplished by allowing the NMOS process to be done either before or after the other technology of interest which cannot be done using commercial Si processes.