Title :
A 64-bit, 2.4 GHz adder with SE detection capabilities employing time redundancy
Author :
Shah, Jaspal Singh ; Jahinuzzman, Shah M. ; Li, David ; Chuang, Pierce ; Sachdev, Manoj
Author_Institution :
Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada
Abstract :
The effect of single event transient is examined in a 64-bit logarithmic adder. Pseudo-static logic (PSL) is proposed to be an area efficient logic choice for time redundant circuit design. The proposed adder is capable of detecting 81% of the errors working at 2.4 GHz consuming 42mW of power. The detection capability comes at the expense of 19% power penalty and negligible area overhead. The results show that soft error detection can be achieved at low cost.
Keywords :
64it; Adder; Pseudo-static Logic; Robust; Single event transient; Soft Error; Time redundant;
Conference_Titel :
Microsystems and Nanoelectronics Research Conference, 2009. MNRC 2009. 2nd
Conference_Location :
Ottawa, ON, Canada
Print_ISBN :
978-1-4244-4751-0
