Thermal analysis of hot spots in advanced 3D-stacked structures

Author

Torregiani, C. ; Vandevelde, B. ; Oprins, H. ; Beyne, E. ; De Wolf, I.

Author_Institution

IMEC, Heverlee, Belgium

fYear

2009

fDate

7-9 Oct. 2009

Firstpage

56

Lastpage

60

Abstract

3D integration architectures for microelectronic circuits have attracted much interest in the recent past, due to their capabilities for more efficient device integration and faster circuit operation. This type of assembly is formed by bonding multiple active layers through a dielectric material, and employs through-silicon vias for electrical interconnection. In this work we present the thermal analysis of a typical 3D-stack, performed by finite element simulations. The effect of the variation of various parameters on the area of influence of a hot spot and on the overall temperature in the stack has been analyzed. We have also investigated the thermal impact of copper studs in the dielectric: the results suggest that Cu studs with a small pitch in the glue can efficiently reduce the temperature in the Si dies.

Keywords

copper; elemental semiconductors; integrated circuit modelling; integrated circuit packaging; microassembling; silicon; thermal analysis; thermal management (packaging); thermal resistance; Cu; Si; advanced 3D-stacked structures; copper studs; die assembly; dielectric glue; dielectric material; finite element simulations; hot spots; silicon dies; thermal analysis; thermal impact; thermal management; thermal resistance; through-silicon vias; Assembly; Bonding; Copper; Dielectric materials; Finite element methods; Integrated circuit interconnections; Microelectronics; Performance analysis; Temperature; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal Investigations of ICs and Systems, 2009. THERMINIC 2009. 15th International Workshop on

Conference_Location

Leuven

Print_ISBN

978-1-4244-5881-3

Type

conf

Filename

5340068