DocumentCode :
505517
Title :
IEC vs. HBM: How to optimize on-chip protections to handle both requirements?
Author :
Lebon, Julien ; Jenicot, Guillaume ; Moens, Peter ; Pogany, Dionyz ; Bychikhin, Sergey
Author_Institution :
Power Technol. Centre, ON Semicond. Belgium, Oudenaarde, Belgium
fYear :
2009
fDate :
Aug. 30 2009-Sept. 4 2009
Firstpage :
1
Lastpage :
6
Abstract :
In automotive products, on-chip ESD protection must withstand both HBM and system ESD pulses. Some unexpected failures at medium current can be explained by current filaments creation for low dissipated power density. Explanation of failure mechanisms and layout optimization, based on TCAD simulation, are proposed.
Keywords :
automotive electronics; bipolar transistors; electrostatic discharge; failure analysis; technology CAD (electronics); HBM; IEC; TCAD simulation; automotive products; current filaments; failure mechanisms; layout optimization; low dissipated power density; on-chip ESD protection; Analytical models; Automotive engineering; Electrostatic discharge; Failure analysis; IEC; Performance evaluation; Protection; Silicon; System-on-a-chip; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
EOS/ESD Symposium, 2009 31st
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-58537-176-1
Electronic_ISBN :
978-1-58537-176-1
Type :
conf
Filename :
5340104
Link To Document :
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