Title :
Self-protection capability of power arrays
Author :
Lafonteese, D. ; Vashchenko, V. ; Linten, D. ; Scholz, M. ; Thijs, S. ; Sawada, M. ; Nakaei, T. ; Hasebe, T. ; Hopper, P. ; Groeseneken, G.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
fDate :
Aug. 30 2009-Sept. 4 2009
Abstract :
A new direct HBM waveform measurement technique is applied to study the self-protection capability of high voltage power arrays under ESD stress. It is demonstrated that the maximum ESD pulse current level an array may safely conduct is a function of the gate driver circuit coupling and array layout design.
Keywords :
driver circuits; electrostatic discharge; power system protection; ESD stress; array layout design; direct HBM waveform measurement; gate driver circuit coupling; high-voltage power arrays; maximum ESD pulse current level; self-protection capability; Circuit testing; Coupling circuits; Driver circuits; Electrostatic discharge; Pins; Protection; Pulse circuits; Pulse measurements; Stress; Voltage;
Conference_Titel :
EOS/ESD Symposium, 2009 31st
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-58537-176-1
Electronic_ISBN :
978-1-58537-176-1
