Title :
System level and hot plug-in protection of high voltage transient pins
Author :
Vashchenko, V.A. ; LaFonteese, D.J.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
fDate :
Aug. 30 2009-Sept. 4 2009
Abstract :
A new high holding voltage lateral PNP device is experimentally demonstrated in a 40 V drain-extended CMOS process, followed by a new compact PNP-SCR device-level solution utilizing a two-stage snapback. The advantage of these lateral DeMOS-based devices is the capability to provide local ESD protection that is robust against transient latch-up for pins with system level, hot swap, and hot plug-in requirements.
Keywords :
CMOS integrated circuits; electrostatic discharge; transients; transmission lines; PNP-SCR device-level solution; drain-extended CMOS process; high-voltage transient pins; hot plug-in protection; hot swap; lateral DeMOS-based devices; local ESD protection; system level; transient latch-up; transmission line pulse characteristics; two-stage snapback; voltage 40 V; CMOS process; CMOS technology; Clamps; Conductivity; Electrostatic discharge; Maintenance; Pins; Power system protection; Robustness; Voltage control;
Conference_Titel :
EOS/ESD Symposium, 2009 31st
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-58537-176-1
Electronic_ISBN :
978-1-58537-176-1
