ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology

Author

Di Sarro, James ; Yang, Yang ; Chatty, Kiran ; Gauthier, Robert ; Ille, Adrien ; Mitra, Souvick ; Li, Junjun ; Russ, Christian ; Rosenbaum, Elyse ; Ioannou, Dimitris

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA

fYear

2009

fDate

Aug. 30 2009-Sept. 4 2009

Firstpage

1

Lastpage

8

Abstract

Gate dielectric breakdown measurements were performed on high-k/metal gate and SiON/polysilicon gate NMOSFETs down to the ESD time domain. Measurements indicate that, for a given NMOSFET on-state performance level, high-k transistors have increased robustness to ESD compared to SiON transistors.

Keywords

CMOS integrated circuits; MOSFET; electrostatic discharge; semiconductor device breakdown; silicon compounds; time-domain analysis; CMOS technology; ESD time-domain characterization; NMOSFETs; SiON; gate dielectric breakdown measurements; high-k gate dielectrics; high-k transistors; metal gate; on-state performance level; polysilicon gate; size 32 nm; CMOS technology; Dielectric breakdown; Dielectric measurements; Electrostatic discharge; High K dielectric materials; High-K gate dielectrics; MOSFETs; Performance evaluation; Time domain analysis; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

EOS/ESD Symposium, 2009 31st

Conference_Location

Anaheim, CA

Print_ISBN

978-1-58537-176-1

Electronic_ISBN

978-1-58537-176-1

Type

conf

Filename

5340124