Title :
An investigation of input protection for CDM robustness in 40nm CMOS technology
Author :
Morishita, Yasuyuki ; Ishizuka, Hiroyasu ; Watanabe, Kentaro ; Hashimoto, Kenji ; Wakai, Nobuyuki ; Hiraoka, Takayuki ; Kumashiro, Shigetaka
Author_Institution :
NEC Sagamihara Plant, MIRAI-Selete, Sagamihara, Japan
fDate :
Aug. 30 2009-Sept. 4 2009
Abstract :
Adiabatic failures due to an initial peak voltage of VF-TLP measurements were observed at the input gate of a 40 nm CMOS technology. Moreover, a correlation was verified between the failure current of the VF-TLP measurements and failure voltage of CDM testing. Through the transient analyses by a VF-TLP system, the performance of a diode-stack was better than that of SCRs as an input protection for CDM robustness.
Keywords :
CMOS integrated circuits; electrostatic discharge; failure analysis; integrated circuit testing; transient analysis; CDM robustness; CMOS technology; VF-TLP measurements; adiabatic failures; diode-stack performance; failure current; failure voltage; size 40 nm; transient analyses; CMOS technology; Circuit testing; Current measurement; Diodes; Electrostatic discharge; Inverters; Protection; Robustness; Variable structure systems; Voltage measurement;
Conference_Titel :
EOS/ESD Symposium, 2009 31st
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-58537-176-1
Electronic_ISBN :
978-1-58537-176-1
