DocumentCode
505554
Title
Electrical and thermal scaling trends for SOI FinFET ESD design
Author
Thijs, S. ; Trémouilles, D. ; Griffoni, A. ; Russ, C. ; Linten, D. ; Scholz, M. ; Collaert, N. ; Rooyackers, R. ; Duvvury, C. ; Groeseneken, G.
Author_Institution
IMEC vzw, Leuven, Belgium
fYear
2009
fDate
Aug. 30 2009-Sept. 4 2009
Firstpage
1
Lastpage
8
Abstract
This paper first presents an analysis of the holding voltage of NMOS and PMOS SOI FinFETs in bipolar mode. Further, to make FinFETs an area-efficient technology option, geometrical parameters which are fixed by the current process will be scaled down. A TCAD simulation methodology is used to predict the robustness of scaled-down FinFETs.
Keywords
MOSFET; electrostatic discharge; silicon-on-insulator; technology CAD (electronics); ESD; NMOS SOI FinFET; PMOS SOI FinFET; TCAD; bipolar mode; electrical scaling; electrostatic discharge; geometrical parameters; holding voltage; thermal scaling; Design engineering; Electrostatic discharge; FinFETs; MOS devices; Predictive models; Robustness; Silicon; Space technology; Tin; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
EOS/ESD Symposium, 2009 31st
Conference_Location
Anaheim, CA
Print_ISBN
978-1-58537-176-1
Electronic_ISBN
978-1-58537-176-1
Type
conf
Filename
5340141
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