Optimal bounded-degree VLSI networks for sorting in a constant number of rounds

Minimum-area VLSI networks have been proposed in, for sorting N elements in O(log N) time. However, the network proposed in has a complex structure, and no explicit network construction was given in. This paper presents new designs of optimal VLSI sorters, which combine rotate-sort with enumeration-sort. One major contribution of this paper is the development of an efficient index-mapping methodology to construct simple reduced-area shuffle networks which are used to permute data between sorting stages. Moreover, the proposed networks are amenable to simple partitioning schemes resulting in multiple chip networks in which each chip has a small number of I/O pins.