Programming costs of explicit memory localization on a large scale shared memory multiprocessor

We present detailed experimental work involving a commercially available large scale shared memory MIMD parallel computer having a software controlled cache coherence mechanism. The implementation of a scalable MIMD computer with hardware-controlled coherent shared hierarchical memory is indeed a formidable task and has yet to be effectively implemented. We present some techniques used to exploit our multiprocessor (the BBN TC2000) on a network simulation program, showing the resulting performance gains and the associated programming costs. We show that an efficient implementation relies heavily on the user´s ability to explicitly manage the memory system, which is typically handled by hardware support on other shared memory multiprocessors.