DocumentCode
5068
Title
System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip
Author
Yaoyao Ye ; Zhehui Wang ; Peng Yang ; Jiang Xu ; Xiaowen Wu ; Xuan Wang ; Nikdast, Mahdi ; Zhe Wang ; Duong, Luan H. K.
Author_Institution
Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China
Volume
33
Issue
11
fYear
2014
fDate
Nov. 2014
Firstpage
1718
Lastpage
1731
Abstract
Multiprocessor systems-on-chip show a trend toward integration of tens and hundreds of processor cores on a single chip. With the development of silicon photonics for short-haul optical communication, wavelength division multiplexing (WDM)-based optical networks-on-chip (ONoCs) are emerging on-chip communication architectures that can potentially offer high bandwidth and power efficiency. Thermal sensitivity of photonic devices is one of the main concerns about the on-chip optical interconnects. We systematically modeled thermal effects in optical links in WDM-based ONoCs. Based on the proposed thermal models, we developed OTemp, an optical thermal effect modeling platform for optical links in both WDM-based ONoCs and single-wavelength ONoCs. OTemp can be used to simulate the power consumption as well as optical power loss for optical links under temperature variations. We use case studies to quantitatively analyze the worst-case power consumption for one wavelength in an eight-wavelength WDM-based optical link under different configurations of low-temperature-dependence techniques. Results show that the worst-case power consumption increases dramatically with on-chip temperature variations. Thermal-based adjustment and optimal device settings can help reduce power consumption under temperature variations. Assume that off-chip vertical-cavity surface-emitting lasers are used as the laser source with WDM channel spacing of 1 nm, if we use thermal-based adjustment with guard rings for channel remapping, the worst-case total power consumption is 6.7 pJ/bit under the maximum temperature variation of 60°C; larger channel spacing would result in a larger worst-case power consumption in this case. If we use thermal-based adjustment without channel remapping, the worst-case total power consumption is around 9.8 pJ/bit under the maximum temperature variation of 60°C; in this case, the worst-case power consumption would benefit from a larger channel spacing.
Keywords
integrated circuit interconnections; integrated circuit modelling; integrated optics; integrated optoelectronics; network-on-chip; optical interconnections; optical links; wavelength division multiplexing; OTemp; WDM channel spacing; WDM-based ONoC; WDM-based optical networks-on-chip; bandwidth efficiency; channel remapping; eight-wavelength WDM-based optical link; low-temperature-dependence technique; maximum temperature variation; multiprocessor system-on-chip; off-chip vertical-cavity surface-emitting lasers; on-chip communication architectures; on-chip optical interconnects; on-chip temperature variation; optical power loss; optical thermal effect modeling platform; optimal device setting; photonic devices; power consumption reduction; power consumption simulation; power efficiency; processor cores; short-haul optical communication; silicon photonics; single-wavelength ONoC; system-level analysis; system-level modeling; temperature 60 degC; temperature variation; thermal sensitivity; thermal-based adjustment; wavelength division multiplexing; worst-case power consumption; worst-case total power consumption; Insertion loss; Optical fiber communication; Optical receivers; Optical sensors; Optical switches; Optical transmitters; Wavelength division multiplexing; Multiprocessor; WDM; optical interconnect; optical network-on-chip; temperature sensitivity; thermal effect;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2014.2351584
Filename
6930846
Link To Document