DocumentCode :
507423
Title :
Voltage binning under process variation
Author :
Zolotov, Vladimir ; Visweswariah, Chandu ; Xiong, Jinjun
Author_Institution :
T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
fYear :
2009
fDate :
2-5 Nov. 2009
Firstpage :
425
Lastpage :
432
Abstract :
Process variation is recognized as a major source of parametric yield loss, which occurs because a fraction of manufactured chips do not satisfy timing or power constraints. On the other hand, both chip performance and chip leakage power depend on supply voltage. This dependence can be used for converting the fraction of too slow or too leaky chips into good ones by adjusting their supply voltage. This technique is called voltage binning. All the manufactured chips are divided into groups (bins) and each group is assigned its individual supply voltage. This paper proposes a statistical technique of yield computation for different voltage binning schemes using results of statistical timing and variational power analysis. The paper formulates and solves the problem of computing optimal supply voltages for a given binning scheme.
Keywords :
integrated circuit design; integrated circuit manufacture; leakage currents; chip leakage power; chip performance; individual supply voltage; manufactured chips; optimal supply voltages; parametric yield loss; power constraints; process variation; statistical technique; statistical timing; variational power analysis; voltage binning; yield computation; Algorithm design and analysis; Costs; Delay; Energy consumption; Frequency; Integrated circuit yield; Leakage current; Manufacturing; Timing; Voltage; Voltage binning; leakage current; parametric yield;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design - Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Print_ISBN :
978-1-60558-800-1
Electronic_ISBN :
1092-3152
Type :
conf
Filename :
5361257
Link To Document :
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