Title :
Research on pipeline R22SDF FFT
Author :
Jian Li ; Feng Liu ; Teng Long ; Erke Mao
Author_Institution :
Radar Res. Lab., Beijing Inst. of Technol., Beijing
Abstract :
The resource utilization of butterflies, multipliers, memory size, and control logic was analyzed according to several pipeline FFT processors. Radix-22 Single-path Delay Feedback (R22SDF) was proposed due to the limit of hardware resource and real-time in ASIC design; gave the scheme, pipeline architecture, flow of BFI and BFII; did Signal to Quantization Noise Ratio (SQNR) simulation for various bit-widths, round or cut off deal per stage, different input/output word lengths; implemented in Xilinx series FPGA V4SX55 with VHDL, did pulse compression in one radar project to verify R22SDF algorithm; R22SDF FFT need the least resource, has high real-time performance, is suitable for VLSI implementation.
Keywords :
VLSI; application specific integrated circuits; fast Fourier transforms; field programmable gate arrays; microprocessor chips; pipeline arithmetic; ASIC design; VHDL; VLSI implementation; Xilinx series FPGA V4SX55; control logic; pipeline FFT processors; pipeline R22SDF FFT; pipeline architecture; radix-22 single-path delay feedback; resource utilization; signal to quantization noise ratio; Pipeline; R22SDF FFT; Real-Time; Resource;
Conference_Titel :
Radar Conference, 2009 IET International
Conference_Location :
Guilin
Print_ISBN :
978-1-84919-010-7
