An efficient 2.4GHz radio frequency identification (RFID) in a standard CMOS process

This paper describes the design of an ultra-low-power analog front-end circuitry for a UHF passive RFID transponder. The design includes a voltage multiplier, a voltage regulator, a demodulator, a power-on-reset, a ring oscillator, a matching network and a backscatter modulator. We present a novel charge-pump circuit for improved voltage gain and power efficiency of RFID tags. The charge pump is fully integrable and takes advantage of both passive and active multiplication to reduce the required input power. The minimum required input power is ¿20.45dBm to generate a 1.2V supply voltage from a 50Ω antenna at 2.4GHz. The voltage multiplier efficiency is 15.95% for a 1MΩ load. The regulator consumes 602nW of DC power and maintains the range of the reference voltage variation to 0.1% while Vdd is varied from 0.8V to 2V. The PSNR of the regulator is -42dB at 2.45GHz frequency and remains greater than -32dB from 100Hz to 10GHz frequencies. The pulse width demodulator is used to extract the input data. The ring oscillator produces a 395 kHz clock for the digital section. Post-layout simulations show the overall power consumption is 1.8μW. The circuit is designed using the low-threshold 0.13μm Atmel CMOS technology. The operating distance of this RFID is in excess of 9 meters based on the regulated 4W EIRP in the US.