DocumentCode
509949
Title
POWER7 multi-core processor design
Author
Sinharoy, Balaram
Author_Institution
IBM Corporation, USA
fYear
2009
fDate
12-16 Dec. 2009
Firstpage
1
Lastpage
1
Abstract
Summary form only given. In this talk, we will describe many key architectural, micro-architectural, RAS and power-management features of the POWER7 core for the first time. POWER7 is IBM´s first 8-core processor chip, with each core capable of 4-way SMT, fabricated in IBM´s 45 nm SOI technology with 11 levels of metal. Details of the processor core will be discussed, along with insights, technical issues and challenges related to designing high performance, power-efficient multi-core chips for building balanced servers.
Keywords
logic design; microprocessor chips; silicon-on-insulator; 8-core processor chip; IBM; POWER7 multicore processor design; SOI technology; power management; power-efficient multicore chips; servers; size 45 nm; Buildings; Computer architecture; Microarchitecture; Multicore processing; Power engineering and energy; Power generation; Process design; Reduced instruction set computing; Surface-mount technology; Technological innovation;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on
Conference_Location
New York, NY
ISSN
1072-4451
Print_ISBN
978-1-60558-798-1
Type
conf
Filename
5375303
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