DocumentCode
509976
Title
Application-aware prioritization mechanisms for on-chip networks
Author
Das, Reetuparna ; Mutlu, Onur ; Moscibroda, Thomas ; Das, Chita R.
Author_Institution
Pennsylvania State Univ., University Park, PA, USA
fYear
2009
fDate
12-16 Dec. 2009
Firstpage
280
Lastpage
291
Abstract
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple applications to efficiently and fairly share the network, to improve system performance. Existing local packet scheduling policies in the routers fail to fully achieve this goal, because they treat every packet equally, regardless of which application issued the packet. This paper proposes prioritization policies and architectural extensions to NoC routers that improve the overall application-level throughput, while ensuring fairness in the network. Our prioritization policies are application-aware, distinguishing applications based on the stall-time criticality of their packets. The idea is to divide processor execution time into phases, rank applications within a phase based on stall-time criticality, and have all routers in the network prioritize packets based on their applications´ ranks. Our scheme also includes techniques that ensure starvation freedom and enable the enforcement of system-level application priorities. We evaluate the proposed prioritization policies on a 64-core CMP with an 8Ã8 mesh NoC, using a suite of 35 diverse applications. For a representative set of case studies, our proposed policy increases average system throughput by 25.6% over age-based arbitration and 18.4% over round-robin arbitration. Averaged over 96 randomly-generated multiprogrammed workload mixes, the proposed policy improves system throughput by 9.1% over the best existing prioritization policy, while also reducing application-level unfairness.
Keywords
microprocessor chips; multiprocessing systems; network routing; network-on-chip; NoC routers; application-aware prioritization mechanisms; many-core processors; network-on-chips; prioritization policies; randomly-generated multiprogrammed workload mixes; stall-time criticality; Algorithm design and analysis; Computer architecture; Computer networks; Delay; Design optimization; Measurement; Network-on-a-chip; Scheduling algorithm; System performance; Throughput; On-chip networks; arbitration; memory systems; multi-core; packet scheduling; prioritization;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on
Conference_Location
New York, NY
ISSN
1072-4451
Print_ISBN
978-1-60558-798-1
Type
conf
Filename
5375387
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