Simulation of surface plasmon and its application in on-chip interconnect for future IC

As the number of transistors integrated on a single processor reaches two billions, Moore´s law faces more challenges than ever as on-chip interconnect becomes a bottleneck for data exchange within the chip. Future increases in bus speed will be difficult due to the heat generated at high frequency along the tiny copper wires. Compared with its electronic counterpart, the optical interconnect is much faster and it has been successfully used in long-haul, metro, LAN, and even board-to-board data communications. When it comes to on-chip data communication, however, optical interconnect becomes very awkward because of the well-know diffraction limit, i.e., its effective size cannot be smaller than one wavelength. There has been significant effort on silicon photonics, which is compatible with CMOS technology and its size can be reduced to 1/3 wavelength, which is about several hundred nanometers. Compared with the current state-of-art microelectronic technology, which is only 32nm reported by Intel recently, this is still about one order of magnitude larger. Therefore, optical interconnect as its current form, could not replace the conventional electronic interconnect.