An Overview of Data Bandwidth Hierarchy for an Embedded Stream Processor

Author

Zongtao, Duan ; Yanni, Zhang ; Zongyuan, Duan

Author_Institution

Inf. Coll., Chang´´an Univ., Xi´´an, China

Volume

1

fYear

2009

fDate

25-27 Dec. 2009

Firstpage

34

Lastpage

36

Abstract

The overall speed of computation is determined not just by the speed of the processor, but also by the ability of the memory system to feed data to it. Imagine is a novel image processor which is constructed by a research group of Stanford University. A brand new data bandwidth hierarchy of this processor is introduced in this article. This new data bandwidth hierarchy is constructed by local register file(LRF), stream register file(SRF) and main memory. LRF is used by the ALU clusters. SRF looks like cache in traditional processor. But SRF is a specific unit in stream processor. SRF is used as a stream load/store unit in stream processor. Using this kind of data bandwidth hierarchy the image processing speed is improved greatly.

Keywords

embedded systems; image processing; microprocessor chips; storage management; data bandwidth hierarchy; embedded stream processor; image processing speed; image processor; local register file; main memory; memory system; stream register file; Arithmetic; Bandwidth; Computer applications; Embedded computing; Feeds; Image processing; Image storage; Parallel processing; Random access memory; Streaming media; Imagine; computer architecture; data bandwidth hierarchy; embedded; image processor; stream processor;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science-Technology and Applications, 2009. IFCSTA '09. International Forum on

Conference_Location

Chongqing

Print_ISBN

978-0-7695-3930-0

Electronic_ISBN

978-1-4244-5423-5

Type

conf

DOI

10.1109/IFCSTA.2009.14

Filename

5385141