High-level statistical static timing analysis under process variation

This paper proposes a promising statistical static timing analysis (SSTA) method for high-level design. The delay models obtained using gate-level SSTA are mapped to a timing graph of functional modules. The timing analysis of a circuit can be performed using the completed timing graph. In experiments, the proposed method showed very slight differences of 2.18% at the 80% timing yield constraint (TYC) and of 0.03% at the 99.87% (3¿) TYC, compared to Monte-Carlo simulation. By considering correlations among functional modules, the proposed method performs accurate timing analysis for high-level design.