An instruction redundancy removal method on a transport triggered architecture processor

As a class of configurable instruction-level parallelism architectures, transport triggered architecture (TTA) processors, with simple but high cost-effective architecture, have more advantage in the field of embedded digital signal processing applications comparing with the general purpose processors. In this paper, an instruction redundancy removal TTA processor with base plus offset addressing load/store function unit (LSFU) and no-operation (NOP) instruction slots reuse is introduced. With the new LSFU, a TTA processor´s addressing ability and flexibility were greatly improved. At the same time, program memory size was saved, because the number of long immediate data in the program was dramatically decreased. Furthermore, the novel NOP instruction slots reuse also shrunk the program memory size by utilizing the waste NOP instruction slots. To evaluate the instruction redundancy removal method, a 32-point DCT benchmark was used. Comparing with the results from a general purpose processor, ARM9E-S, and a traditional TTA processor published before, it shows significant efficiency improvement in our design.