The novel high efficiency on chip transformers for the CMOS power amplifier

This paper proposes a novel on chip transformer for the purpose of combining output voltage of the high power amplifier in a standard 0.13-¿m TSMC CMOS technology. The transformer adopts multi-finger architecture which provides low insertion loss and allows high current capacity on the transformer. The proposed transformer is estimated and designed by 3-D electromagnetic simulator. Due to the multi-finger structure, the voltage transfer efficiency from input to output at the transformer reaches 81%. To enhance linearity of the PA, cross coupled compensation capacitors are added. With all integration of transformers, baluns, and paralell 4 diff-amps, the prototype class AB power amplifier shows 30 dBm saturation power with 1.8 V supply voltage and 35 dBm with 3 V supply voltage at 2.4 GHz. The output P1dB is 27 dBm with 18% drain efficiency and 30 dBm with 15.6% drain efficiency.