An automatic test approach for field programmable gate array (FPGA)

Test for a FPGA is supposed to consist of two steps, namely configuration and fault scan. The process of configuration and fault scan is required to be repeated many times before all resources of a FPGA-under-test are covered. Traditional test schemes for a FPGA-under-test involve a large amount of manual work. An automatic test approach for a FPGA-under-test implemented by an in-house SOC co-verification technology based FPGA functional test system is proposed and presented in the paper. This test system has taken advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware. Experimental result demonstrates that the approach of automatic test scheme yields advantages over traditional ones.