Local Mismatch in 45nm digital clock networks

Local mismatch is one of the challenges facing the microelectronics industry in scaling of transistors. Smaller feature size leads to increased mismatch that causes larger variations in timing properties, which in turn can limit the achievable design frequency or complexity. High speed and low power designs are particularly sensitive to these types of variations. In this work, we have tried to characterize the impact of mismatch in clock networks considering various scenarios and propose a set of guidelines to reduce the probability of timing failures. We have shown that the effect of mismatch is not negligible but it can be reduced to a manageable limit.