Symbolic techniques for statistical timing analysis of RCL mesh networks with resistor loops

Author

Hao, Zhigang ; Shi, Guoyong

Author_Institution

Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China

fYear

2009

fDate

14-16 Dec. 2009

Firstpage

470

Lastpage

473

Abstract

A symbolic moment calculator for recursive moment computation of RCL interconnect networks involving resistor loops is proposed. Using the tearing technique, the network can be partitioned into a spanning tree and a set of resistor links. Special data structures for symbolic moment analysis are proposed. Applications of this structural computation methodology to symbolic reduced order modeling and statistical timing analysis of mesh networks are investigated.

Keywords

VLSI; network analysis; resistors; statistical analysis; symbol manipulation; timing; tree data structures; RCL interconnect networks; RCL mesh networks; VLSI; data structures; recursive moment computation; resistor loops; spanning tree; statistical timing analysis; structural computation methodology; symbolic moment calculator; symbolic techniques; tearing technique; Circuit synthesis; Clocks; Computer networks; Crosstalk; Data structures; Integrated circuit interconnections; Mesh networks; Resistors; Statistical analysis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on

Conference_Location

Singapore

Print_ISBN

978-9-8108-2468-6

Type

conf

Filename

5403880