DocumentCode
511817
Title
Performance verification of folded-cascode amplifiers built from nanowire transistors
Author
Ye Shuqin ; Juanda ; Bernal, Olivier Daniel ; Minkyu Je ; Zhiming Chen
Author_Institution
Integrated Circuits & Syst. Lab., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear
2009
fDate
14-16 Dec. 2009
Firstpage
376
Lastpage
380
Abstract
For the first time, this paper investigates the plausibility of building analog amplifiers from nanowire (NW) transistors and verifies their performances. First, since the models for nanowire transistors have not been developed yet, drain current formulae are fitted into conventional and 1.8 power law models for single transistors. Second, open-loop gain of one folded-cascode amplifier is obtained from the measured closed-loop gain with power supply of 1.5 V and DC bias current of 1 ¿A and open-loop gain is also calculated using the developed formulae, which verifies the measurement result. Third, the lowest supply voltage of 0.75 V is obtained for another two-stage folded-cascode amplifier. Although more work still needs to be done in this area, the results show a promising future in analog applications of NW transistors.
Keywords
amplifiers; analogue circuits; nanowires; transistors; DC bias current; analog amplifiers; closed-loop gain; current 1 muA; drain current formulae; folded-cascode amplifier verification; nanowire transistors; open-loop gain; power law models; voltage 0.75 V; voltage 1.5 V; Analog integrated circuits; Current measurement; Energy consumption; Gain measurement; Integrated circuit technology; Laboratories; Microelectronics; Power measurement; Power supplies; Voltage; Nanowire (NW) transistors; gate-all-around (GAA) transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on
Conference_Location
Singapore
Print_ISBN
978-9-8108-2468-6
Type
conf
Filename
5403884
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