A novel 1.2 Gbps LVDS receiver for multi-channel applications

This paper presents a new LVDS clock and data recovery (CDR) circuit for use in multi-channel applications. Combining a deskewing module together with a novel sampling clock generator achieves immunity to skew effects between channels as well as collective jitter due to process, power supply, and temperature variations. Besides, by dynamically tracking eye edges and introducing different strategies for eye edges occurring at different regions, the proposed circuit can generate sampling clocks aligned to middle of the data eye, and hence offers maximum amount of timing margin and improved jitter tolerance. The proposed CDR circuit has been designed in a TSMC 90 nm CMOS process. Simulation results demonstrate that when skew plus jitter jumping around 0.3 UI and 0 UI points for the input 2¹¹-1 pseudorandom bit sequences (PRBS), the circuit can recover correctly data at frequency from 175 MHz to 1.2 GHz.