High-speed, low switching noise and load adaptive output buffer

Author

Lin, Yingyan ; Zou, Xuecheng ; Zheng, Zhaoxiao ; Huo, Wenjie ; Chen, Xiaofei ; Kang, Wenjing

Author_Institution

Dept. of Electron. Sci. & Technol., Huazhong Univ. of Sci. & Technol., Wuhan, China

fYear

2009

fDate

14-16 Dec. 2009

Firstpage

280

Lastpage

282

Abstract

A new output buffer with low switching noise and load adaptability is designed based on a TSMC 90 nm CMOS technology. The proposed buffer can reduce switching noise induced on supply lines and output ringing while achieving very fast output transitions. Moreover, the load adaptive method is simple and effective. Simulation results demonstrate that the proposed buffer achieves 4.1%-53.5% improvements in ground bounce and 2.9%- 15.2% reductions in output ringing compared with those of the AC/DC buffer. Meanwhile, it reduces ground bounce by 6.5%- 17.6% and output ringing by 3.8%- 10.9% relative to the CSR buffer.

Keywords

CMOS logic circuits; buffer circuits; integrated circuit noise; TSMC CMOS technology; ground bounce; load adaptability; output buffer; output ringing; size 90 nm; switching noise; Buffer storage; CMOS technology; Circuit noise; Crosstalk; Delay; Noise reduction; Power supplies; Semiconductor device noise; Switches; Transmission lines; Ground bounce; load adaptability; output buffer; output ringing; switching noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on

Conference_Location

Singapore

Print_ISBN

978-9-8108-2468-6

Type

conf

Filename

5403888