A 20MHz switched-current sample-and-hold circuit for current mode analog iterative decoders

A high-frequency low-power switched-current (SI) sample-and-hold (S/H) of a current-mode analog iterative decoder is proposed. A capacitor divider is used to reduce charge injection from the sampling switch and a cascode transistor is used to reduce channel length modulation. The cascode transistor is biased by a CMOS peaking current source rather than the conventional CMOS Widlar current source to arrive at stable S/H operation. The SI S/H is designed using a 0.35 ¿m CMOS process, and simulation results show that it could operate at 20 MHz, consuming a power of only 22.275 ¿W.