High-accuracy and power-efficient switched-current memory cell

In this paper, a simple technique to realize a switched-current memory cell with high accuracy and power efficiency is presented. By setting the memory transistors in triode region, this design reduces distortions due to threshold voltage mismatch as well as clock feedthrough. These characteristics are deduced from theory and verified by simulations. Designed in a 0.18-¿m CMOS process, the switched-current memory cell achieves a simulated performance of over 93.26 dB SINAD at the sampling rate of 2 MS/s with the input signal at the Nyquist frequency of 0.999 MHz. The power consumption is 242 ¿W with a 128 ¿A input current range.