Bit-serial systolic architecture for 2-D non-separable discrete wavelet transform

In this paper, we have presented a bit-serial systolic-like architecture for the computation of non-separable two-dimensional discrete wavelet transform (2-D DWT) based on the principle of distributed arithmetic. The computational core of the proposed structure is highly regular and modular. The computations which become redundant due to the decimation process are eliminated to obtain a low-complexity computing algorithm for the 2-D DWT. Moreover, it exploits the advantage of constant wavelet filter-base in the DA-based structure to reduce the hardware-complexity. It is shown that the proposed structure involves very low hardware complexity, and significantly less area-time complexity compared with the existing bit-level designs.