Digital pixel sensor with on-line spatial and temporal compression scheme

In this paper, the concept of compressive acquisitive image sensor is extended to the temporal domain. Architecture of a compact CMOS image sensor designed based on the design paradigm capture¿compress¿store is proposed. The image sensor array is divided into quadrants. Spatial compression algorithm is integrated into quadrant-level circuit and carried out on-line before the storage phase. All the quadrants are further classified into background/non-background quadrants by an off-array adaptive judge logic. A reference array is built in the off-array logic to adaptively tracking the movement between frames. Temporal redundance between frames are removed in the readout phase. Experimental results show that the proposed algorithm enables more than 50% memory saving at a PSNR level of 27 dB with around 0.5 BPP.