Using structured ASIC to improve design productivity

Author

Tsai, Yu-Wen ; Wu, Kun-Chen ; Tung, Hui-Hsiang ; Lin, Rung-Bin

Author_Institution

Faraday Technol. Corp., Hsinchu, Taiwan

fYear

2009

fDate

14-16 Dec. 2009

Firstpage

25

Lastpage

28

Abstract

Structured ASIC is a well-developed technology that enables a shorter design Turn-Around-Time (TAT) as well as less non-recurring-engineering (NRE) cost for very deep submicron designs. Since 2003, Faraday technology has developed its own structured ASIC solutions. Based on its own competitive technology architecture, Faraday has proposed platform-based SoC solutions and realized more than 100 customer projects using its structured ASIC technology. This paper presents Faraday´s experience of using structured ASICs and shows Faraday´s efforts to establish a high-productivity structured ASIC flow.

Keywords

application specific integrated circuits; integrated circuit design; system-on-chip; Faraday technology; competitive technology architecture; high productivity structured ASIC flow; nonrecurring engineering cost; platform-based SoC solutions; structured ASIC solutions; very deep submicron designs; Application specific integrated circuits; CMOS technology; Computer science; Costs; Design engineering; Field programmable gate arrays; Libraries; Productivity; System-on-a-chip; Time to market; NRE; Structured ASIC; TAT;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on

Conference_Location

Singapore

Print_ISBN

978-9-8108-2468-6

Type

conf

Filename

5403937