Via-configurable logic block architectures for standard cell like structured ASICs

In this paper, we investigate via-configurable logic block (VCLB) architectures of different granularities and logic styles for standard-cell like structured ASIC. VCLB granularity ranges from a few to tens of transistors. Logic styles include those realized using series-parallel transistors and look-up table. VCLBs are designed to enable a standard cell design style so that we can establish a structured ASIC design flow using most of the existing tools. VCLBs are employed to construct cell libraries, each consisting of a few tens of cells to several hundred cells. This broad spectrum of VCLB architectures is evaluated in terms of delay, power, and area of designs.