Design of a 21 GHz UWB differential low noise amplifier using .13µm CMOS process

Author

Rashid, S.M.S. ; Roy, Apratim ; Ali, S.N. ; Rashid, A.B.M.H.

Author_Institution

Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh

fYear

2009

fDate

14-16 Dec. 2009

Firstpage

538

Lastpage

541

Abstract

This paper presents the design of a 21 GHz UWB differential low noise amplifier. The circuit is designed in IBM .13 μm CMOS process and is simulated in Cadence Spectre. The forward gain of the circuit is 9.72 dB at 21 GHz with a bandwidth of 4 GHz (from 19 GHz to 23 GHz). Reverse isolation is less than -26.4 dB and the input-output matching parameters are -26 dB and -19.5 dB respectively. Noise figure of the LNA is 4.4 dB at the center frequency. The amplifier is driven by a 1.2 V power supply and consumes only 20.76 mW power. To the best of the authors´ knowledge, UWB differential low noise amplifier operating above 20 GHz is rarely reported.

Keywords

CMOS analogue integrated circuits; integrated circuit design; low noise amplifiers; microwave amplifiers; ultra wideband technology; CMOS process; Cadence Spectre simulation; LNA; UWB differential low noise amplifier; bandwidth 4 GHz; center frequency; frequency 21 GHz; input-output matching parameters; noise figure; noise figure 4.4 dB; power 20.76 mW; reverse isolation; size 0.13 μm; voltage 1.2 V; 21 GHz; Amplifier; Differential; LNA; Low Noise; Passive Matching; Single Stage; UWB;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on

Conference_Location

Singapore

Print_ISBN

978-9-8108-2468-6

Type

conf

Filename

5403943