An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power

A new ultra low-power CMOS Electromyograph (EMG) amplifier is presented in this paper. It is based on the application of a novel capacitive load reduction circuit technique to the capacitive-reset switched-capacitor circuit architecture. This is achieved by adding a capacitor in series with the capacitive load of the amplifier so as to reduce the total effective load capacitance being seen by the op-amp for reducing power driving requirement. The amplifier is designed using CSM 1.8 V 0.18 ¿m triple-well CMOS process technology and simulated using realistic BSIM3 models. The amplifier dissipates only 15.14 ¿W at a dual power supply of ±0.9 V. It has has a gain of 40 dB at dc and 38.5 dB at 3.2 kHz. The estimated passband input-referred noise is 2.08 ¿V_rms.