Effect of variability in SWCNT-based logic gates

This work is concerned with carbon nanotube diameter variations and the resulting uncertainties on the behavior of logic gates made from single walled carbon nanotubes (SWCNTs). Monte Carlo simulations were performed for logic gates based on CNTs of different mean diameters using the Stanford CNFET model. Delay characteristics of logic gates (NOT, NAND, NOR) are studied. This work reveals that logic gates employing SWCNTs with mean diameters greater than about 1.2 nm, show less variation in their timing characteristics, provided that a CNT diameter standard deviation of less than 0.1nm can be guaranteed by a technology process.