Reuse of a HW/SW coverification environment during the refinement process of a functional C model down to an executable HW/SW specification

Author

Winterholer, Markus ; Schäfer, Florian

Author_Institution

R&D, Cadence Design Syst., CTS, Feldkirchen, Germany

fYear

2009

fDate

22-24 Sept. 2009

Firstpage

1

Lastpage

4

Abstract

This paper presents a method reusing a coverification system testbench throughout the refinement process starting from a functional C model of a distributed system with the goal to optimize the HW/SW partitioning and distribution to multiple cores of a system. The partitioned system can then be used as an executable HW/SW specification in the ensuing design flow. The presented paradigm was validated using a distributed brake-by-wire design for the automotive industry.

Keywords

C language; automobile industry; brakes; formal specification; formal verification; hardware-software codesign; HW/SW coverification environment; HW/SW partitioning; automotive industry; coverification system testbench; distributed brake-by-wire design; distributed system; ensuing design flow; executable HW/SW specification; functional C model; partitioned system; refinement process; Communication system control; Computer architecture; Coordinate measuring machines; Hardware; Performance evaluation; Read only memory; Software performance; System performance; System-level design; Testing; co-verification; hw/sw co-design; partitioning;

fLanguage

English

Publisher

ieee

Conference_Titel

Specification & Design Languages, 2009. FDL 2009. Forum on

Conference_Location

Sophia Antipolis

ISSN

1636-9874

Electronic_ISBN

1636-9874

Type

conf

Filename

5404046