Presentation of new architecture for reduction of power dissipation in nano hybrid chip

In this paper we present an architecture for nanowire layer in FPNI which is include switch boxes concept. The FPNI improves the Field-Programmable Gate Array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches which decreases both the area and power consumption of the circuit. In this paper we present an approach to building an FPNI chip which is similar to CMOS FPGA. By applying genetic algorithm optimization tool, a delay optimized circuit is implemented in FPNI. The power dissipation in two chips are compared to emphasize the benefits of this new architecture.